MODEL-BASED RULE TABLE GENERATION

摘要

Provided is a method for fabricating a semiconductor device including receiving an integrated circuit (IC) layout pattern, for example, from a design house. In some embodiments, a process simulation model is utilized to generate a freeform layout pattern by an inverse lithography technology (ILT) process. The process simulation model is configured to simulate processing conditions for the IC layout pattern. In various embodiments, the freeform layout pattern is associated with the IC layout pattern. In some examples, a simplified layout pattern is generated, where the simplified layout pattern is an approximation of the freeform layout pattern. Thereafter, sub-resolution assist feature (SRAF) rules, based on the simplified layout pattern, may be calculated and an SRAF rule table may be generated.

主权项

1. A method of semiconductor device fabrication, comprising:
receiving an integrated circuit (IC) layout pattern; utilizing a process simulation model configured to simulate processing conditions for the IC layout pattern, generating a second layout pattern by a model-based (MB) mask correction process, wherein the second layout pattern is associated with the IC layout pattern; generating a third layout pattern that is an approximation of the second layout pattern; and calculating sub-resolution assist feature (SRAF) rules based on the third layout pattern.