发明名称 演算処理装置及び演算処理装置の制御方法
摘要 A core executing processes in plural threads specifies one gate to read out a state of the gate from a thread progress control unit holding information of plural gates disposed in a loop state, setting a state of a gate disposed subsequently relative to a gate when a state of the gate is set to a first state to a second state, and setting the state of the gate to the first state when a certain period of time elapses from a first request of reading the state for the gate which is set to the second state, by every certain process in each thread. The core executes a next process when the state of the specified gate is the first state, and makes the execution of the next process wait until the state becomes the first state when it is not the first state.
申请公布号 JP6079518(B2) 申请公布日期 2017.02.15
申请号 JP20130188579 申请日期 2013.09.11
申请人 富士通株式会社 发明人 成瀬 彰
分类号 G06F9/52;G06F15/80 主分类号 G06F9/52
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