发明名称 Read operations and circuits for memory devices having programmable elements, including programmable resistance elements
摘要 A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
申请公布号 US9570166(B1) 申请公布日期 2017.02.14
申请号 US201414572646 申请日期 2014.12.16
申请人 Adesto Technologies Corporation 发明人 Gilbert Nad Edward;Naveh Ishai;Derhacobian Narbeh
分类号 G11C11/00;G11C13/00;G11C11/56 主分类号 G11C11/00
代理机构 代理人
主权项 1. A memory device, comprising: a sense circuit configured to generate a sense result by sensing a state of a memory element; a store circuit configured to store a plurality of sense results generated at different times by the sense circuit for a same memory element; and an evaluation circuit that generates an output value for the memory element in response to at least the plurality of sense results for the memory element stored in the store circuit.
地址 Santa Clara CA US