发明名称 INTERCONNECT ROUTING CONFIGURATIONS AND ASSOCIATED TECHNIQUES
摘要 Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
申请公布号 US2017040264(A1) 申请公布日期 2017.02.09
申请号 US201615297005 申请日期 2016.10.18
申请人 Intel Corporation 发明人 Qian Zhiguo;Aygun Kemal;Kim Dae-Woo
分类号 H01L23/538;H01L21/48;H01L25/065;H01L23/00 主分类号 H01L23/538
代理机构 代理人
主权项 1. An apparatus comprising: a substrate; a first routing layer disposed on the substrate and having a first plurality of traces, wherein a first ground trace of the first plurality of traces has a first width as measured in a direction parallel to a face of the substrate, and a first signal trace of the first plurality of traces has a second width as measured in the direction parallel to the face of the substrate; and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a second ground trace of the second plurality of traces has the first width, and a second signal trace of the second plurality of traces has the second width.
地址 Santa Clara CA US