| 摘要 |
This invention addresses the problem of using vertical transistors, namely surrounding gate transistors (SGTs), to provide a small-surface-area semiconductor device that constitutes a CMOS two-input NAND circuit. This invention provides a semiconductor device constituting a two-input NAND circuit that has a small surface area and comprises a row of four MOS transistors. Each of said MOS transistors is formed on top of a flat silicon layer formed on top of a substrate and has a structure in which a drain, a gate, and a source are laid out vertically, said gate surrounding a silicon pillar, wherein the flat silicon layer comprises a first activated region that has a first conductivity type and a second activated region that has a second conductivity type, said regions being connected to each other via a silicon layer formed on the surface of the flat silicon layer. |
