发明名称 |
SEMICONDUCTOR DEVICE HAVING A MULTI-LEVEL INTERCONNECTION STRUCTURE |
摘要 |
A semiconductor device includes a semiconductor substrate, and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another. Each interconnection layer includes a real interconnection and a dummy interconnection covered with an insulative film. The interconnection layers include a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view. |
申请公布号 |
US2017033041(A1) |
申请公布日期 |
2017.02.02 |
申请号 |
US201514813781 |
申请日期 |
2015.07.30 |
申请人 |
ROHM CO., LTD. |
发明人 |
MORITA Takeshi |
分类号 |
H01L23/528;H01L23/522 |
主分类号 |
H01L23/528 |
代理机构 |
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代理人 |
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主权项 |
1. A semiconductor device, comprising:
a semiconductor substrate; and a multi-level interconnection structure that is provided on the semiconductor substrate and that has a plurality of interconnection layers stacked one on another, each interconnection layer including a real interconnection and a dummy interconnection covered with an insulative film; wherein the plurality of interconnection layers includes a first interconnection layer including a first real interconnection, a second interconnection layer stacked on the first interconnection layer and including an overlapping dummy interconnection that overlaps the first real interconnection in a stacking direction of the plurality of interconnection layers in a sectional view, and a third interconnection layer stacked on the second interconnection layer and including a second real interconnection that overlaps the overlapping dummy interconnection in the stacking direction of the plurality of interconnection layers in the sectional view. |
地址 |
Kyoto JP |