发明名称 |
MEMORY SYSTEM, INFORMATION PROCESSING SYSTEM, AND HOST DEVICE |
摘要 |
An embodiment provides a memory system connectable to a host device. The memory system includes a host interface configured to receive a read command and a write command and a first non-volatile memory. In addition, the memory system includes a debug unit configured to collect debugging information when a processor executes firmware. The debug unit is capable of outputting the debugging information to a buffer area of the host device through the host interface. |
申请公布号 |
US2017024266(A1) |
申请公布日期 |
2017.01.26 |
申请号 |
US201615066664 |
申请日期 |
2016.03.10 |
申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
IWAI Daisuke |
分类号 |
G06F11/07 |
主分类号 |
G06F11/07 |
代理机构 |
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代理人 |
|
主权项 |
1. A memory system connectable to a host device, the memory system comprising:
a host interface configured to receive a read command and a write command; a first non-volatile memory configured to read data in response to the read command and to store data in response to the write command; a debug unit configured to collect debugging information; and a processor configured to execute firmware to control the memory system, the firmware having a function of receiving a debug command and a function of setting a buffer address to the debug unit, the buffer address indicating a buffer area allocated on a memory in the host device, wherein the debug unit is capable of outputting the debugging information to the buffer area through the host interface when the processor executes the firmware. |
地址 |
Minato-ku JP |