| 发明名称 | Packet processing apparatus and packet processing method | ||
| 摘要 | A packet processing apparatus includes a processor configured to execute a process. The process includes: determining a memory from which packets are read, out of a first memory that stores the packets and a second memory that stores the packets, in accordance with number of pointers indicative of storage locations of the packets in the first memory; and reading the packets stored at the storage locations indicated by the pointers, from the memory determined at the determining. | ||
| 申请公布号 | US9544229(B2) | 申请公布日期 | 2017.01.10 |
| 申请号 | US201514661354 | 申请日期 | 2015.03.18 |
| 申请人 | FUJITSU LIMITED | 发明人 | Kitada Atsushi |
| 分类号 | G06F12/00;H04L12/747;G11C8/12 | 主分类号 | G06F12/00 |
| 代理机构 | Fujitsu Patent Center | 代理人 | Fujitsu Patent Center |
| 主权项 | 1. A packet processing apparatus comprising: a processor configured to execute a process including: determining a memory from which packets are read, out of a first memory that stores the packets and a second memory that stores the packets, in accordance with a number of pointers indicative of storage locations of the packets in the first memory; and reading the packets stored at the storage locations indicated by the pointers, from the memory determined at the determining, wherein the determining includes, not actually reading the pointers in a buffer which has not been read-accessed, but skipping read addresses of the pointers by the number of pointers in another buffer which has actually been read. | ||
| 地址 | Kawasaki JP | ||