CONVOLUTIONAL NEURAL NETWORKS ON HARDWARE ACCELERATORS

摘要

A hardware acceleration component is provided for implementing a convolutional neural network. The hardware acceleration component includes a N-row and M-column array of functional units, N input data buffers to store input data, and M weights data buffers to store weights data. Each of the N input data buffers is coupled to a corresponding one of the N rows of functional units. Each of the M weights data buffers is coupled to a corresponding one of the M columns of functional units. Each functional unit in a row receives a same set of input data. Each functional unit in a column receives a same set of weights data from the weights data buffer coupled to the row. Each of the functional units performs a convolution of the received input data and the received weights data, and the M columns of functional units provide M planes of output data.