发明名称 |
SEMICONDUCTOR DEVICE |
摘要 |
A semiconductor device having stable electric characteristics is provided. The transistor includes first to third oxide semiconductor layers, a gate electrode, and a gate insulating layer. The second oxide semiconductor layer has a portion positioned between the first and third oxide semiconductor layers. The gate insulating layer has a region in contact with a top surface of the third oxide semiconductor layer. The gate electrode overlaps with a top surface of the portion with the gate insulating layer positioned therebetween. The gate electrode faces a side surface of the portion in a channel width direction with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm. The length in the channel width direction of the second oxide semiconductor layer is less than 60 nm. |
申请公布号 |
US2017005202(A1) |
申请公布日期 |
2017.01.05 |
申请号 |
US201615264667 |
申请日期 |
2016.09.14 |
申请人 |
Semiconductor Energy Laboratory Co., Ltd. |
发明人 |
KOBAYASHI Yoshiyuki;MATSUDA Shinpei;YAMAZAKI Shunpei |
分类号 |
H01L29/786 |
主分类号 |
H01L29/786 |
代理机构 |
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代理人 |
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主权项 |
1. A transistor comprising:
a first oxide semiconductor layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a gate insulating layer over and in contact with the third oxide semiconductor layer; and a gate electrode over the gate insulating layer; wherein a portion of the gate electrode faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer positioned therebetween, wherein the portion of the gate electrode extends below a bottom surface of the second oxide semiconductor layer in a depth direction, wherein the second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 20 nm, and wherein a length of the second oxide semiconductor layer in the channel width direction is less than 80 nm. |
地址 |
Atsugi-shi JP |