| 摘要 |
As store instructions arrive 205 at the load store unit (LSU), the LSU determines 215, based on the destination address 211 for example, whether a counter is allocated to a cache line affected by each store. If not, the LSU allocates 220 a counter. If so, the LSU updates 217 the counter. Also, in response to a store instruction affecting a cache line neighbouring or adjacent to a cache line that has a counter 225 that meets a condition 227 such as a threshold, the LSU characterises that store instruction as one to be effected without obtaining ownership 230 of the affected cache line, and provides that store to be serviced by an element of the shared memory hierarchy, such as an L2 cache. This may reduce churn in a private L1 cache, i.e. cache pollution, when a memory copy operation, or an operation with a similar store pattern, is performed. |
