发明名称 QUIESCENT STATE RETENTION MODE FOR PROCESSOR
摘要 A quiescent state retention mode (QSRM) permits minimal power consumption and dissipation by an electronic device while idle without producing adverse latencies to users or causing system instability. Upon a call to enter the QSRM, processes may be frozen, clocks may be gated, switching regulators may be placed in low power mode, SDRAM may be placed into self-refresh mode, caches may be flushed, IRQs may be disabled, and the system waits for interrupt to wakeup. In the QSRM, powered components include the switching regulator configured to provide power to the processor is maintained in a low power mode while the SDRAM is placed in self-refresh.
申请公布号 EP2446338(A4) 申请公布日期 2016.05.25
申请号 EP20100792547 申请日期 2010.06.18
申请人 AMAZON TECHNOLOGIES, INC. 发明人 LACHWANI, MANISH;BERBESSOU, DAVID
分类号 G06F1/26;G06F1/32 主分类号 G06F1/26
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