发明名称 |
ANTI-FUSE TYPE ONE-TIME PROGRAMMABLE MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME |
摘要 |
An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor. |
申请公布号 |
US2016141049(A1) |
申请公布日期 |
2016.05.19 |
申请号 |
US201514697355 |
申请日期 |
2015.04.27 |
申请人 |
SK hynix Inc. |
发明人 |
SONG Hyun Min |
分类号 |
G11C17/16 |
主分类号 |
G11C17/16 |
代理机构 |
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代理人 |
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主权项 |
1. An anti-fuse type one-time programmable (OTP) memory cell array including a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, the anti-fuse type OTP memory cell array comprising:
a plurality of well regions respectively disposed in the plurality of rows; a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the plurality of well regions; a plurality of source/drain regions respectively disposed in portions of the well regions between the plurality of anti-fuse gates; and a plurality of drain regions respectively disposed in the well regions located at one side of a last anti-fuse gate disposed in a last column, which is opposite to a first anti-fuse gate disposed in a first column, wherein each of the unit cells includes one anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor. |
地址 |
Gyeonggi-do KR |