Microprocessor that makes 64-bit general purpose registers available in MSR address space while operating in non-64-bit mode

摘要

A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes.

主权项

1. A microprocessor, comprising:
hardware registers that instantiate the IA-32 Architecture EDX and EAX general purpose registers (GPRs); and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs; wherein the microprocessor associates with each of the R8-R15 GPRs a respective unique Model Specific Register (MSR) address; wherein in response to an IA-32 Architecture Read from Model Specific Register (RDMSR) instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers.