Shift register and display device having the same

摘要

A shift register 10 is configured such that m unit circuits 11 each including a shift unit 12 and three buffer units 13r, 13g, and 13b are in a multi-stage cascade connection and that 3m signals in total including three signals from each stage are outputted. The m shift units 12 perform a shift operation, and a first signal Y is outputted from each stage. When a clock signal CK is at a high level, the first signal Y rises higher than a normal high level due to bootstrapping. The buffer unit 13r controls an output signal YR to be at a high level based on the buffer control signal CR and the first signal Y. A buffer control circuit 7 controls buffer control signals CR, CG, and CB to be at a high level for a time period shorter than a half cycle of the clock signal. With this, a shift register with a reduced circuit amount and low power consumption is provided.

主权项

1. A shift register, comprising:
a buffer control circuit configured to output at least three buffer control signals; and a plurality of unit circuits in a multi-stage cascade connection and capable of outputting at least four signals from each stage according to the buffer control signals and a clock signal which is different from the buffer control signals, wherein each of the unit circuits includes a shift unit which operates in accordance with the clock signal and at least three buffer units, each corresponding to one of the buffer control signals, the shift unit includes:
a first transistor configured to apply an ON potential to a first node according to a set signal;a second transistor configured to apply an OFF potential to the first node according to a reset signal;a third transistor provided between an input node for the clock signal and a second node, and having a control terminal connected to the first node; anda fourth transistor configured to apply an OFF potential to the second node according to the reset signal, each of the at least three buffer units includes:
an output node;a fifth transistor configured to apply an ON potential to the output node based on a potential at the first node and a corresponding buffer control signal; anda sixth transistor configured to apply an OFF potential to the output node according to the reset signal, each of the at least three buffer units is configured to output an output signal from the output node, the shift unit is configured to output a signal on the second node as the set signal of a next-stage unit circuit and the reset signal of a previous-stage unit circuit, the buffer control circuit is configured to control the buffer control signals to be at an ON level for a time period shorter than a half cycle of the dock signal, and the buffer control circuit controls the buffer control signals to be at an ON level respectively for periods not overlapping with each other, the period being included in an ON-level period of the clock signal in a horizontal period and to be at an OFF level before the clock change to an OFF level.