Peak voltage detector and related method of generating an envelope voltage

摘要

A peak detector circuit receives an oscillating power supply signal. A capacitor is selectably coupled to the signal and charged to a value corresponding to a peak value of the signal. A switch is then opened to isolate the capacitor. When the signal rises to within a selected threshold, relative to the stored value, a comparator produces a command signal to close the switch, again coupling the capacitor to the signal. The peak detector can also include a tracking circuit that controls the capacitor to track the oscillating signal while the switch is closed, a timer circuit that closes the switch and activates the tracking circuit if more than a selected time passes without production of a command signal, a circuit that controls the polarity of a leakage current of the capacitor, a further auxiliary capacitor and a further auxiliary switch with a further control logic.

主权项

1. An integrated detector, comprising:
a rectifying circuit, having an input and an output, configured to generate an rectified voltage at the output corresponding to an oscillating voltage at the input; a first integrated capacitor configured to store an envelope voltage representing a detected peak value of the oscillating voltage; a first switch configured to electrically couple said first integrated capacitor to the output of the rectifying circuit when the first switch is closed, and to isolate the integrated capacitor from the rectifying circuit when the first switch is open; an auxiliary integrated capacitor configured to store an auxiliary voltage representing a last detected peak value of the oscillating voltage; a second switch configured to electrically couple said auxiliary integrated capacitor to the output of the rectifying circuit when the second switch is closed, and to isolate the auxiliary integrated capacitor from the rectifying circuit when the second switch is open; a comparator configured to compare the auxiliary voltage with the oscillating voltage, to generate a first command signal adapted to close said second switch in response to determining that a difference between the auxiliary voltage and the oscillating voltage is smaller than a first offset voltage, and to keep the second switch open in response to determining that the difference is greater than the first offset voltage; a logic circuit configured to receive said first command signal and including a timer configured to be enabled by an active switching edge of said first command signal and to force low an auxiliary command signal for a fixed period when a first pre-established time interval has elapsed from said active switching edge; said timer being configured to generate a pulse flag of a pre-established duration when a second pre-established time interval longer than said first pre-established time interval has elapsed from said active switching edge; a first logic element configured to close the second switch when said first command signal is logically active or when said pulse flag is generated, and to open the second switch otherwise; an auxiliary logic element configured to close the first switch when said auxiliary command signal is logically active and, at the same time, said first command signal or said pulse flag is logically active and to open the first switch otherwise.