Source synchronous bus signal alignment compensation mechanism

摘要

An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

主权项

1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
a replica distribution network, configured to receive a first signal, and configured to generate a second signal, wherein said replica distribution network comprises replicated propagation lengths, loads, and buffering of a radial distribution network for a strobe, and wherein said radial distribution network equalizes all propagation paths for said strobe as it is distributed; and a bit lag control element, configured to measure a propagation time beginning with assertion of said first signal and ending with assertion of said second signal, and configured to generate a first value on a lag bus that indicates an adjusted propagation time, said bit lag control element comprising:
delay lock control, configured to select one of a plurality of successively delayed versions of said first signal that coincides with said assertion said second signal, and configured to generate a second value on a lag select bus that indicates said propagation time;adjust logic, coupled to a circuit and to said lag select bus, configured adjust said second value by an amount prescribed by said circuit to yield a third value that is output to an adjusted lag bus; anda gray encoder, configured to gray encode said third value to generate said first value on said lag bus.