发明名称 |
Method of manufacturing three-dimensional semiconductor device and variable resistive memory device |
摘要 |
A three-dimensional semiconductor device, a resistive variable memory device including the same, and a method of manufacturing the same are provided. The method may include forming a source on a semiconductor substrate, sequentially forming a first semiconductor layer formed of a first material, a second semiconductor layer formed of a second material having a higher oxidation rate than that of the first material, and a third semiconductor layer formed of the first material on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; forming a lightly doped drain (LDD) region in the second semiconductor layer and a drain in the third semiconductor layer; oxidizing outer circumferences of the first semiconductor layer, the LDD region and the drain region to form a gate insulating layer; forming a gate on an outer circumference of the gate insulating layer to overlap the first semiconductor layer and a portion of the LDD region; foaming a heating electrode on the drain; and forming a variable resistance layer on the heating electrode. |
申请公布号 |
US9318576(B2) |
申请公布日期 |
2016.04.19 |
申请号 |
US201414573795 |
申请日期 |
2014.12.17 |
申请人 |
SK Hynix Inc. |
发明人 |
Park Nam Kyun |
分类号 |
H01L21/336;H01L29/66;H01L27/24;H01L29/78;H01L27/22 |
主分类号 |
H01L21/336 |
代理机构 |
IP & T Group LLP |
代理人 |
IP & T Group LLP |
主权项 |
1. A method of manufacturing a three-dimensional (3D) semiconductor device, the method comprising:
forming a source on a semiconductor substrate; sequentially forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, on the source; patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer to form an active pillar; oxidizing an outer circumference of the active pillar to form a gate insulating layer; and forming a gate on an outer circumference of the gate insulating layer, wherein the second semiconductor layer is formed of a material having a higher oxidation rate than those of the first semiconductor layer and the third semiconductor layer. |
地址 |
Gyeonggi-do KR |