Method and system for modeling a flip-flop of a user design

摘要

The present patent document relates to a method and apparatus for modeling a flip-flop of a user's circuit design when that circuit design is mapped in a hardware functional verification system including a plurality of interconnected emulation chips, or in a single emulation chip. The flip flop can be modeled in the emulation chip as two stages using only a single instruction, and may be configured by programming a register set. A data block, enable block, and LUT block are provided to model the flip flop, and may operate in one of several modes, including combined and uncombined modes. The data block includes a data array to store and provide previous data inputs and previous states of the modeled flip flop. The disclosed embodiments allow a more efficient use of LUTs for modeling flip flops, including options for resets and global enables, operating in several modes.

主权项

1. A processor-based hardware functional verification system into which a circuit design may be mapped, wherein the circuit design includes a flip flop to be modeled in an emulation chip of the system, comprising:
a data block to select one of a plurality of data inputs generated by a plurality of emulation processors of the hardware functional verification system as a current data input of the modeled flip flop, wherein the data block includes a data array comprising a memory to store a previously-selected data input of the modeled flip flop; an enable block to generate one or more enable signals, at least one of the one or more enable signals being output to the data block; and a lookup table (LUT) block that receives either the current data input or a previous data input of the modeled flip flop based on at least one of the one or more enable signals, the LUT further receives the one or more enable signals from the enable block, the LUT generates a state output signal of the modeled flip flop according to the one or more enable signals, the state output signal of the modeled flip being either a previous output of the modeled flip flop or a new output of the modeled flip flop.