PROCESSOR AND PROCESSING METHOD OF VECTOR INSTRUCTION

摘要

A processor includes: a plurality of pipelines including a first pipeline and a second pipeline and configured to pipeline-process vector instructions including load instructions with respect to a memory, and when an instruction issuance controller configured to decode a vector instruction read out from an instruction memory and issue instructions to the pipelines issues a first load instruction with respect to a first region of a memory to the first pipeline and a second load instruction with respect to the first region of the memory is being processed in the second pipeline, a processing order in the first load instruction in the first pipeline is changed on the basis of an offset value determined according to a number of cycles that have been processed already in the second load instruction so that an access address of the first load instruction matches an access address of the second load instruction.

主权项

1. A processor, comprising:
a plurality of pipelines configured to pipeline-process vector instructions including load instructions for reading data from a memory, the plurality of pipelines including a first pipeline and a second pipeline; an instruction issuance controller configured to decode a vector instruction read out from an instruction memory and issue the vector instruction to the pipeline; and a controller, when the instruction issuance controller issues a first load instruction with respect to a first region of a memory to the first pipeline and a second load instruction with respect to the first region of the memory is being processed in the second pipeline, configured to determine an offset value according to a number of cycles that have been processed already in the second load instruction so that an access address of the first load instruction to the memory matches an access address of the second load instruction to the memory, and change a processing order in the first load instruction in the first pipeline on the basis of the offset value.