Power gating for three dimensional integrated circuits (3DIC)

摘要

Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

主权项

1. A three dimensional integrated circuit (3DIC) structure in a semiconductor die comprising:
a first power gating cell (PGC) formed on a first active device layer; a first interconnect structure formed over the first active device layer, wherein the first interconnect structure connects the first PGC to a power source; a first virtual power circuit formed on a second active device layer; and a second interconnect structure formed between the first PGC and the first virtual power circuit, wherein the second interconnect structure electrically connects the first PGC and the first virtual power circuit.