Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance

摘要

Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers.

主权项

1. A resolution enhancement method for wafer geometry measurements, the method comprising:
acquiring a plurality of wafer geometry images for at least one substantially identical portion of at least one wafer, wherein each of the plurality of wafer geometry images is acquired with a different sub-pixel modulation in spatial phase; and jointly processing the plurality of wafer geometry images utilizing at least one statistical treatment to produce a resolution-enhanced representation of the plurality of wafer geometry images.