Fast normalization in a mixed precision floating-point unit

摘要

A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.

主权项

1. A method for returning scalar single precision denormal results to double precision normal results in architected format with limited latency impact on performance utilizing an improved floating-point unit architecture, the method comprising:
performing a first normalization on a first unrounded single precision denormal result of a floating-point operation, wherein the first normalization includes performing fraction leading zero removal and exponent adjustment up to a minimum exponent threshold on the first unrounded single precision denormal result to yield a second unrounded single precision denormal result, wherein performing the first normalization includes utilizing a first normalizer circuit of the improved floating-point unit architecture; counting leading zeros of the second unrounded single precision denormal result; performing fraction rounding of the second unrounded single precision denormal result to yield a rounded single precision denormal result, wherein performing fraction rounding includes utilizing a floating-point unit rounder circuit of the improved floating-point unit architecture; pre-computing a first exponent and a second exponent for the second unrounded single precision denormal result in parallel with a second normalization of the rounded single precision denormal result, wherein pre-computing includes utilizing a floating-point unit subtractor circuit of the improved floating-point unit architecture; and outputting a final fraction result by performing the second normalization of the rounded single precision denormal result back to architected format, wherein performing the second normalization includes utilizing a second normalizer circuit of the improved floating-point unit architecture; wherein the architected format includes the final fraction result and one of the first exponent and the second exponent.