Chip scale packages and related methods

摘要

A chip scale package (CSP) includes a die and a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead. The first surface of the first lead forms a first plane. A second lead is mechanically coupled to a second surface of the die at a first surface of the second lead. The first surface of the second lead forms a second plane. A mold compound at least partially encapsulates the die, forming a CSP. The first plane and the second plane are oriented substantially perpendicularly to a third plane formed by a motherboard surface when the CSP is coupled to the motherboard surface. The CSP includes no wirebonds and the first lead and second lead are on opposing surfaces of the CSP. The third plane of the motherboard may be a largest planar surface of the motherboard.

主权项

1. A chip scale package (CSP), comprising:
a die; a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead, the first surface of the first lead forming a first plane and a second surface of the first lead forming a fifth plane, a thickness of the first lead present between the first plane and the fifth plane; a second lead mechanically coupled to a second surface of the die at a first surface of the second lead, the first surface of the second lead forming a second plane and a second surface of the second lead forming a fourth plane, a thickness of the second lead present between the second plane and the fourth plane; and a mold compound at least partially encapsulating the die, where the die, first lead, second lead, and mold compound form a chip scale package (CSP); wherein the first plane of the first lead and the second plane of the second lead are oriented substantially perpendicularly to a third plane formed by a motherboard when the CSP is coupled to the motherboard at the thickness of the first lead and the thickness of the second lead.