| 发明名称 |
MEMORY DEVICE |
| 摘要 |
A memory device according to an embodiment includes a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer. |
| 申请公布号 |
US2016064452(A1) |
申请公布日期 |
2016.03.03 |
| 申请号 |
US201514594782 |
申请日期 |
2015.01.12 |
| 申请人 |
KABUSHIKI KAISHA TOSHIBA |
发明人 |
UEDA Yoshihiro;NAKAI Tsukasa;KONDO Masaki;TAJIMA Hikari;TOKUHIRA Hiroki;IZUMIDA Takashi |
| 分类号 |
H01L27/24;H01L43/02;G11C29/04;H01L45/00;G11C11/16;G11C13/00;H01L27/22;H01L43/08 |
主分类号 |
H01L27/24 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A memory device comprising:
a memory element; and a transistor including a semiconductor layer and a plurality of gates, wherein the plurality of gates include: a first set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, and a second set of gates, the gates being disposed in a manner to sandwich the semiconductor layer, the gates included in the first set is disposed in a manner to separate from the gates included in the second set in a direction along a side surface of the semiconductor layer, and when the transistor is turned on, at least a gate on one side of the semiconductor layer in the first set is activated, and at least a gate on the other side of the semiconductor layer in the second set is activated. |
| 地址 |
Tokyo JP |
