发明名称 BIASED ESD CIRCUIT
摘要 This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
申请公布号 US2016064374(A1) 申请公布日期 2016.03.03
申请号 US201514834554 申请日期 2015.08.25
申请人 Fairchild Semiconductor Corporation 发明人 Snowdon Kenneth P.;Kang Taeghyun;Li Yongliang
分类号 H01L27/02;H01L49/02;H02H9/04;H01L27/06 主分类号 H01L27/02
代理机构 代理人
主权项 1. A biased electrostatic discharge (ESD) circuit, comprising: an ESD device including a gate terminal, a source terminal, a drain terminal, and a bulk terminal, wherein the ESD device is configured to provide an ESD discharge path between the drain terminal and the source terminal, wherein the bulk terminal of the ESD device is configured to receive negative bias to reduce the drain terminal to source terminal capacitance of the ESD device.
地址 San Jose CA US