Integrated circuit clock tree visualizer

摘要

A system that visualizes a clock tree for an integrated circuit receives an extracted cell library, an extracted clock netlist including clock headers and interconnects, and simulation results. The system generates an internal data structure for the clock headers, and divides the clock headers into a plurality of levels based on the interconnects. The system then orders the clock headers from a lowest level to a highest level, and displays the ordered clock headers in an untangled manner.

主权项

1. A non-transitory computer-readable medium having instructions stored thereon that, when executed by a processor, cause the processor to visualize a clock tree for an integrated circuit, the visualizing comprising:
receiving an extracted cell library, an extracted text-based clock netlist of an integrated circuit design comprising clock headers and interconnects, and simulation results of the integrated circuit design; generating an internal data structure for the clock headers; dividing the clock headers into a plurality of levels based on the interconnects; ordering the clock headers from a lowest level to a highest level, wherein the ordering untangles the interconnects; and displaying on a graphical user interface the ordered clock headers and the untangled interconnects of the integrated circuit design.