发明名称 |
METHOD FOR DECOMPOSING A HARDWARE MODEL AND FOR ACCELERATING FORMAL VERIFICATION OF THE HARDWARE MODEL |
摘要 |
Described is a method performed by a computing device, the method comprises: deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the at least one hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance. |
申请公布号 |
US2016055287(A1) |
申请公布日期 |
2016.02.25 |
申请号 |
US201414463857 |
申请日期 |
2014.08.20 |
申请人 |
HARTUNG ROBERT;GLUECK MATTHIAS |
发明人 |
HARTUNG ROBERT;GLUECK MATTHIAS |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
1. A method performed by a computing device, the method comprising:
deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance. |
地址 |
Braunschweig, NI DE |