Heterogeneous memory system

摘要

A heterogeneous memory system includes a network interface card, a main memory arrangement, a first-level cache, and a memory management unit (MMU). The main memory arrangement, first-level cache and the MMU are disposed on the network interface card. The first-level cache includes an SRAM arrangement and a DRAM arrangement. The MMU is configured and arranged to read first data from the main memory arrangement in response to a stored first value associated with the first data and indicative of a start time. The MMU selects one of the SRAM arrangement or the DRAM arrangement for storage of the first data and stores the first data in the selected one of the SRAM arrangement or DRAM arrangement. The MMU reads second data from one of the SRAM arrangement or DRAM arrangement and writes the data to the main memory arrangement in response to a stored second value associated with the second data and indicative of a duration.

主权项

1. A heterogeneous memory system, comprising:
a network interface card; a main memory arrangement disposed on the network interface card; a first-level cache for caching data from the main memory arrangement, the first-level cache disposed on the network interface card and including an SRAM arrangement and a DRAM arrangement; a memory management unit (MMU) disposed on the network interface card and coupled to the SRAM arrangement, the DRAM arrangement, and to the main memory arrangement, the memory management unit configured and arranged to:
read a first data set from the main memory arrangement in response to a stored first value associated with the first data set, the stored first value indicative of a start time relative to initiation of execution of a program that accesses the first data set;select one of the SRAM arrangement or the DRAM arrangement in the first-level cache for storage of the first data set;store the first data set in the selected one of the SRAM arrangement or DRAM arrangement; andread a second data set from one of the SRAM arrangement or DRAM arrangement and write the data to the main memory arrangement in response to a stored second value associated with the second data set, the stored second value indicative of a duration for which the second data set is accessed during execution of the program.