发明名称 PREFETCHING INSTRUCTIONS IN A DATA PROCESSING APPARATUS
摘要 A data processing apparatus has prefetch circuitry for prefetching cache lines of instructions into an instruction cache. A prefetch lookup table is provided for storing prefetch entries, with each entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the corresponding region from which processing circuitry accessed an instruction on a previous occasion. When the processing circuitry executes an instruction from a new region, the prefetch circuitry looks up the table, and if it stores a prefetch entry for the new region, then the at least one block identified by the corresponding entry is prefetched into the cache.
申请公布号 US2016019065(A1) 申请公布日期 2016.01.21
申请号 US201414333889 申请日期 2014.07.17
申请人 ARM Limited 发明人 HAYENGA Mitchell Bryan;EMMONS Christopher Daniel
分类号 G06F9/38 主分类号 G06F9/38
代理机构 代理人
主权项 1. A data processing apparatus comprising: prefetch circuitry configured to prefetch cache lines comprising one or more instructions from a memory to store the prefetched cache lines in an instruction cache; and a prefetch lookup table configured to store a plurality of prefetch entries, each prefetch entry corresponding to a region of a memory address space and identifying at least one block of one or more cache lines within the region from which an instruction was accessed in the instruction cache by processing circuitry on a previous occasion; wherein: in response to the processing circuitry executing an instruction from a new region of the memory address space, the prefetch circuitry is configured to perform a prefetch lookup operation comprising determining whether the prefetch lookup table stores a target prefetch entry corresponding to the new region, and if the prefetch lookup table stores the target prefetch entry, prefetching said at least one block identified by the target prefetch entry.
地址 Cambridge GB