Low-noise flexible frequency clock generation from two fixed-frequency references

摘要

A number of methods and clock generator units are disclosed to produce low Phase Noise clocks for use in Radio Frequency systems. The methods and clock generator units all use two reference clocks: a frequency-accurate reference that has comparatively high Phase Noise, and a frequency-inaccurate reference such as that from a BAW or MEMS clock source that has comparatively low Phase Noise. By combining multiple Phase-Locked Loops and a mixer, it is possible to produce flexible output frequencies whose frequency accuracy is derived from the first reference clock but whose Phase Noise level is derived from the second reference clock, all in a readily-integrated and relatively low-cost system.

主权项

1. A clock generator unit to generate a target clock signal having a target frequency, the clock generator unit comprising:
a Fractional-N phase-locked loop (FNPLL) circuit having:
first phase detector circuitry having a FNPLL reference input terminal and a FNPLL feedback input terminal, the FNPLL reference input terminal to receive a first clock signal, the first clock signal having associated thereto first clock signal Phase Noise;first voltage-controlled oscillator (VCO) circuitry operationally connected to the first phase detector circuitry, the first VCO circuitry to receive an output from the first phase detector circuitry;mixer circuitry to receive a second clock signal and an output signal from the first VCO circuitry, the second clock signal being unrelated to the first clock signal, the mixer circuitry to generate a mixer output signal that comprises a sum signal and a difference signal, the sum signal being at a sum frequency that is a function of a sum of the frequency of the second clock signal and the frequency of the output signal of the first VCO circuitry, the difference signal being at a difference frequency that is a function a difference between the frequency of the second clock signal and the frequency of the output signal of the first VCO circuitry; andfilter circuitry operationally connected to the mixer circuitry, the filter circuitry to receive the mixer output signal and to generate an intermediate signal that is a function of the sum signal,
the FNPLL circuit configured to have a FNPLL bandwidth that filters out the first clock signal Phase Noise and to generate the intermediate clock signal with the intermediate clock signal being substantially free of the first clock signal Phase Noise,and an Integer-N PLL (INPLL) circuit having second phase detector circuitry and second VCO circuitry operationally connected to the second phase detector circuitry, the second phase detector circuitry having an INPLL reference input terminal and an INPLL feedback input terminal, the INPLL reference input terminal to receive the intermediate clock signal, the second VCO circuitry to output the target clock signal, the INPLL circuit being configured to have an INPLL bandwidth that filters out Phase Noise generated by the second VCO circuitry, the INPLL feedback input terminal configured to receive an INPLL feedback signal that is a function of the target clock signal, the FNPLL feedback input terminal configured to receive a FNPLL feedback signal that is also function of the target clock signal.