| 主权项 |
1. A liquid crystal display comprising:
a liquid crystal display panel including data lines, which number less than a horizontal resolution, gate lines crossing the data lines, and subpixels that are arranged in a matrix structure, each of the subpixels being successively charged to data voltages of different colors; a data driving circuit configured to convert digital video data into positive and negative data voltages, supply the positive and negative data voltages to the data lines, and cause the data voltages supplied to the same data line to have the same polarity during one frame period; a gate driving circuit configured to sequentially supply a gate pulse to the gate lines; and a timing controller configured to supply the digital video data to the data driving circuit and control an operation timing of each of the data driving circuit and the gate driving circuit, wherein the subpixels include first and second subpixels positioned adjacent to each other in a first row, and third and fourth subpixels positioned adjacent to each other in a second row, one of the third and fourth subpixels being positioned adjacent to one of the first and second subpixels in a column direction, two gate lines extending between the one of the first and second subpixels and the one of the third and fourth subpixels, wherein the first subpixel is successively charged to the data voltages of two different colors having the same polarity from an ith data line in response to a jth gate pulse, where ‘i’ and ‘j’ are a natural number, wherein the second subpixel is successively charged to the data voltages of two different colors having the same polarity from the ith data line in response to a (j+1)th gate pulse, and the third and fourth subpixels are connected to the ith data line, wherein a drain electrode of a thin film transistor (TFT) in the other one of the third and fourth subpixels crosses over one of the two gate lines and is connected to the ith data line at a position between the two gate lines, and wherein the first, second, third and fourth sub-pixels are connected to the same ith data line and are connected to a ith gate line, a (j+1) gate line, a (i+2) gate line, and a (j+3) gate line, respectively, the first and second subpixels are disposed on opposing sides of the ith date line with the ith date line extending therebetween, and the third and fourth subpixels are disposed at one side of the ith data line with no data line extending therebetween. |
