Semiconductor device, driving method thereof, and electronic appliance

摘要

A semiconductor device in which operation delay due to stop and restart of the supply of a power supply potential is suppressed is provided. Potentials corresponding to data held in first and second nodes while the supply of a power supply potential is continued are backed up in third and fourth nodes while the supply of the power supply potential is stopped. After the supply of the power supply potential is restarted, data are restored to the first and second nodes by utilizing a change in channel resistance of a transistor whose gate is electrically connected to the third or fourth node. Note that shoot-through current is suppressed at the time of data restoration by electrically disconnecting the power supply potential and the first or second node from each other.

主权项

1. A semiconductor device comprising:
first to third circuits, wherein the first circuit comprises first and second nodes, first and second transistors, and first and second wirings, wherein the second circuit comprises third to eighth transistors, third to fourth nodes, and a third wiring, wherein the third circuit comprises first and second NAND circuits and first and second inverter circuits, wherein the first node is capable of holding one of a first potential and a second potential, wherein the second node is capable of holding the other of the first potential and the second potential, wherein the first transistor is capable of controlling electrical continuity between the second node and the first wiring, wherein the second transistor is capable of controlling electrical continuity between the first node and the second wiring, wherein the first and second wirings are supplied with the first potential, wherein the first node is electrically connected to the third node via the third transistor, wherein the first node is electrically connected to the third wiring via the seventh and eighth transistors, wherein the second node is electrically connected to the fourth node via the sixth transistor, wherein the second node is electrically connected to the third wiring via the fourth and fifth transistors, wherein a gate of the fourth transistor is electrically connected to the third node, wherein a gate of the seventh transistor is electrically connected to the fourth node, wherein a first signal is input to a gate of the fifth transistor and a gate of the eighth transistor, wherein the third wiring is supplied with the second potential, wherein the first signal is input to a first input terminal of the first NAND circuit, wherein a second input terminal of the first NAND circuit is electrically connected to the third node, wherein an output terminal of the first NAND circuit is electrically connected to a gate of the first transistor via the first inverter circuit, wherein the first signal is input to a first input terminal of the second NAND circuit, wherein a second input terminal of the second NAND circuit is electrically connected to the fourth node, wherein an output terminal of the second NAND circuit is electrically connected to a gate of the second transistor via the second inverter circuit, and wherein the third and sixth transistors each comprise an oxide semiconductor in a channel formation region.