MULTIPLE VALUED DYNAMIC RANDOM ACCESS MEMORY CELL AND CELL ARRAY USING SINGLE ELECTRON TRANSISTOR

摘要

A multiple valued DRAM cell using a single electron transistor and a cell array are provided to reduce a standby current by refreshing a data value stored in a single electron transistor on fixed cycles. A data value through a bit line is delivered to a switching transistor(M1, M2). When the switching transistor is turned on, a storage capacitor(Cs) is connected to a charge storage node in which a charge is supplied, and stores the data value. One terminal of a load current transistor(M4) is connected to the charge storage node. The load current transistor controls a current supply from a current source to the single electron transistor. One terminal of a voltage control transistor(M5) is connected to the charge storage node. The other terminal of the voltage control transistor is connected to the single electron transistor. The voltage control transistor is connected to the load current transistor, and controls a terminal voltage of the single electron transistor. One terminal of the single electron transistor is connected to the voltage control transistor. The other terminal of the voltage control transistor is connected to a power supply. A gate is connected to the charge storage node. A refresh signal part(SSG, SSO) supplies a refresh signal for recharging the storage capacitor to each transistor.