发明名称 DATA PROCESSING UNIT AND METHOD FOR CONTROLLING CACHE
摘要 <p>On a multiprocessor device, a cache line of a cache memory on each processor is divided into a plurality of partial writable regions. Each processor is given a partial exclusive right which is the exclusive right for each partial writable region. On a cache tag (30) of the cache memory, partial writing status PM is registered onto a cache status (32) of an entry (31) for registration of information on the partial writable regions. Setting of the partial exclusive right eliminates false sharing.</p>
申请公布号 WO2008155844(A1) 申请公布日期 2008.12.24
申请号 WO2007JP62444 申请日期 2007.06.20
申请人 FUJITSU LIMITED;UKAI, MASAKI 发明人 UKAI, MASAKI
分类号 G06F12/08 主分类号 G06F12/08
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