发明名称 TIMING SIGNAL GENERATING CIRCUIT
摘要 <p>PURPOSE:To alter the contents of a timing signal freely within a specific range through program operation, etc., and widen a use range by storing plural timing sequences in an ROM. CONSTITUTION:Plural timing sequences are stored in the ROM5. Consequently, a selection signal (g) for selecting some timing sequence is inputted from a CPU to an input terminal A11 of the ROM5 through an interface circuit (selecting circuit) 7 to select the necessary timing sequence. Then, data with high and low levels are read out seccessively according to addresses from a timing sequence selected by the output signal indicating the counted value of a counter 2 which counts a clock signal, and outputted as a timing signal K. Thus, the signal (f) inputted from the CPU to the ROM5 through the circuit 7 is varied to set plural kinds of signal K freely, widening the use range of a timing signal generating circuit.</p>
申请公布号 JPS59231624(A) 申请公布日期 1984.12.26
申请号 JP19830105307 申请日期 1983.06.13
申请人 TOSHIBA KK 发明人 YAMAGISHI TAKASHI;YAMANE MASANORI
分类号 G06F1/06;G01R31/3183;G06F1/04 主分类号 G06F1/06
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