发明名称 Semiconductor device having hierarchical structured bit line
摘要 A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained.
申请公布号 US2011134678(A1) 申请公布日期 2011.06.09
申请号 US20100926693 申请日期 2010.12.03
申请人 ELPIDA MEMORY, INC. 发明人 SATO TAKENORI;KAJIGAYA KAZUHIKO;YANAGAWA YOSHIMITSU;SEKIGUCHI TOMONORI;KOTABE AKIRA;AKIYAMA SATORU
分类号 G11C5/06 主分类号 G11C5/06
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