发明名称 SEMICONDUCTOR MULTI-PACKAGE MODULE HAVING WIRE BOND INTERCONNECT BETWEEN STACKED PACKAGES
摘要 <P>PROBLEM TO BE SOLVED: To enable pretesting of each package, and increase final test yields of product MPMs. <P>SOLUTION: A semiconductor multi-package module having stacked lower and upper packages, each package including a die attached to a substrate, in which the upper and lower substrates are interconnected by wire bonding. Also, a method for making a semiconductor multi-package module provides a lower molded package including a lower substrate and a die, affixes an upper molded package including an upper substrate onto the upper surface of the lower package, and forms z-axis interconnects between the upper and the lower substrates. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011181971(A) 申请公布日期 2011.09.15
申请号 JP20110137096 申请日期 2011.06.21
申请人 STATS CHIPPAC INC 发明人 KARNEZOS MARCOS
分类号 H01L23/12;H01L25/10;H01L25/11;H01L25/18 主分类号 H01L23/12
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