| 摘要 |
<P>PROBLEM TO BE SOLVED: To effectively prevent characteristic deterioration due to a pattern shift in gate formation while suppressing increase in cell area, and to reduce resistance in a power supply voltage feeder line. <P>SOLUTION: Two inverters respectively composed of first conductivity type driving transistors Qn1 and Qn2 and second conductivity type load transistors Qp1 and Qp2 which are electrically connected in series between a first power supply voltage feeder line VSS and a second power supply voltage feeder line VSS and of which gates are connected in common and cross-connecting input and output are included in each memory cell. At least one of the first power supply voltage feeder line VSS and the second power supply voltage feeder line VSS is composed of a groove wiring obtained by filling the inside of a through groove of an inter-layer insulating layer with conductive material. <P>COPYRIGHT: (C)2012,JPO&INPIT |
