| 主权项 |
1. An integrated circuit within a semiconductor chip, comprising:
a first transistor of a first transistor type having a gate electrode, a first diffusion terminal of a first diffusion type, and a second diffusion terminal of the first diffusion type; a second transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a third transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a fourth transistor of the first transistor type having a gate electrode, a first diffusion terminal of the first diffusion type, and a second diffusion terminal of the first diffusion type; a first transistor of a second transistor type having a gate electrode, a first diffusion terminal of a second diffusion type, and a second diffusion terminal of the second diffusion type; a second transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type; a third transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type; a fourth transistor of the second transistor type having a gate electrode, a first diffusion terminal of the second diffusion type, and a second diffusion terminal of the second diffusion type, both the gate electrode of the first transistor of the first transistor type and the gate electrode of the first transistor of the second transistor type formed by a first linear-shaped conductive structure, the gate electrode of the first transistor of the first transistor type electrically connected to the gate electrode of the first transistor of the second transistor type through the first linear-shaped conductive structure, the first linear-shaped conductive structure having a length as measured in a first direction, the first linear-shaped conductive structure having a top surface that is substantially flat along the length of the first linear-shaped conductive structure, the gate electrode of the second transistor of the first transistor type formed by a second linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the second linear-shaped conductive structure is of the first transistor type, the second linear-shaped conductive structure having a length as measured in the first direction, the second linear-shaped conductive structure having a top surface that is substantially flat along the length of the second linear-shaped conductive structure, the gate electrode of the second transistor of the second transistor type formed by a third linear-shaped conductive structure, wherein any transistor having its gate electrode formed by the third linear-shaped conductive structure is of the second transistor type, the third linear-shaped conductive structure having a length as measured in the first direction, the third linear-shaped conductive structure having a top surface that is substantially flat along the length of the third linear-shaped conductive structure, the first, second, and third linear-shaped conductive structures oriented to extend lengthwise in the first direction, the top surfaces of the first, second, and third linear-shaped conductive structures co-planar with each other, the first linear-shaped conductive structure positioned between the second and third linear-shaped conductive structures in a second direction perpendicular to the first direction, the first, second, third, and fourth transistors of the first transistor type forming a first collection of transistors, the first, second, third, and fourth transistors of the second transistor type forming a second collection of transistors, the first collection of transistors separated from the second collection of transistors by an inner region that does not include a source or a drain of any transistor, the first and second transistors of the first transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the first transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the first transistor of the first transistor type also electrically connected to a common node, the first diffusion terminal of the second transistor of the first transistor type also electrically connected to the common node, the first and second transistors of the second transistor type positioned adjacent to each other, the first diffusion terminal of the first transistor of the second transistor type electrically and physically connected to the first diffusion terminal of the second transistor of the second transistor type, the first diffusion terminal of the first transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the second transistor of the second transistor type also electrically connected to the common node, the first diffusion terminal of the third transistor of the first transistor type electrically connected to the second diffusion terminal of the first transistor of the first transistor type, the first diffusion terminal of the fourth transistor of the first transistor type electrically connected to the second diffusion terminal of the second transistor of the first transistor type, the first diffusion terminal of the third transistor of the second transistor type electrically connected to the second diffusion terminal of the first transistor of the second transistor type, the first diffusion terminal of the fourth transistor of the second transistor type electrically connected to the second diffusion terminal of the second transistor of the second transistor type, the gate electrode of the third transistor of the first transistor type electrically connected to the gate electrode of the fourth transistor of the second transistor type, the gate electrode of the third transistor of the second transistor type electrically connected to the gate electrode of the fourth transistor of the first transistor type; a first interconnect conductive structure located within a first interconnect chip level of the semiconductor chip, the first interconnect chip level formed above a level of the semiconductor chip that includes the first, second, and third linear-shaped conductive structures, the first interconnect chip level separated from the top surfaces of the first, second, and third linear-shaped conductive structures by at least one dielectric material; a second interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the second interconnect conductive structure physically separate from the first interconnect conductive structure; a third interconnect conductive structure located within the first interconnect chip level of the semiconductor chip, the third interconnect conductive structure physically separate from the first interconnect conductive structure; a first gate contact in contact with the first linear-shaped conductive structure, the first gate contact substantially centered in the second direction on the first linear-shaped conductive structure, the first gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the first linear-shaped conductive structure through a dielectric material to contact the first interconnect conductive structure; a second gate contact in contact with the second linear-shaped conductive structure, the second gate contact substantially centered in the second direction on the second linear-shaped conductive structure, the second gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the second linear-shaped conductive structure through the dielectric material to contact the second interconnect conductive structure; a third gate contact in contact with the third linear-shaped conductive structure, the third gate contact substantially centered in the second direction on the third linear-shaped conductive structure, the third gate contact formed to extend in the vertical direction substantially perpendicular to the substrate of the semiconductor chip from the third linear-shaped conductive structure through the dielectric material to contact the third interconnect conductive structure, wherein both the second gate contact and the third gate contact are parts of an electrical connection extending between the second linear-shaped conductive structure and the third linear-shaped conductive structure, the integrated circuit being part of a digital logic circuit. |
