发明名称 Circuit And Method For Monolithic Stacked Integrated Circuit Testing
摘要 A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.
申请公布号 US2015355277(A1) 申请公布日期 2015.12.10
申请号 US201514828174 申请日期 2015.08.17
申请人 Taiwan Semiconductor Manufacturing Company, Ltd. 发明人 Goel Sandeep Kumar;Mehta Ashok
分类号 G01R31/3177 主分类号 G01R31/3177
代理机构 代理人
主权项 1. A monolithic stacked integrated circuit (IC) comprising a known-good-layer (KGL) test circuit in a first layer of the IC, the KGL test circuit comprising: first and second control elements; a first input, to receive a first scan data; a scan segment, to receive the first scan data from the first input and to shift the first scan data to an output of the scan segment; a first multiplexer, to select between the first input and the output of the scan segment in response to a value of the first control element; a first output, coupled to an output of the first multiplexer and to send the first scan data to a second layer; a second input, to receive a second scan data from the second layer; a second multiplexer, to select between the second input and the output of the first multiplexer in response to a value of the second control element; and a second output, coupled to an output of the second multiplexer.
地址 Hsin-Chu TW