| 发明名称 |
CONTACT RESISTANCE OPTIMIZATION VIA EPI GROWTH ENGINEERING |
| 摘要 |
A transistor contact structure and methods of making the same. The method includes forming a first semiconductor layer in a source/drain opening of a substrate, the first layer having a non-planar top surface; forming a second semiconductor layer directly on the first layer, the second layer having a defect density greater than the first layer; and forming a silicide region formed with the second layer, the silicide region having a non-planar interface with the first layer. A portion of the silicide interface may be higher than a top surface of the substrate and another portion may be below. |
| 申请公布号 |
US2015349068(A1) |
申请公布日期 |
2015.12.03 |
| 申请号 |
US201414287506 |
申请日期 |
2014.05.27 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Levesque Annie;Ontalus Viorel C.;Stoker Matthew W. |
| 分类号 |
H01L29/417;H01L21/283;H01L29/66;H01L29/45 |
主分类号 |
H01L29/417 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A contact structure for a transistor comprising:
a semiconductor substrate having an opening; a first semiconductor layer in the opening; a silicide of a metal and a second semiconductor layer wherein the silicide is in contact with the first semiconductor layer; and a non-planar silicide interface comprising a silicide-first semiconductor layer interface. |
| 地址 |
Armonk NY US |
