SYSTEMS AND METHODS FOR IMPLEMENTING A TAG-LESS SHARED CACHE AND A LARGER BACKING CACHE

摘要

A computer processing system includes a plurality of nodes, each node having at least one processor core and at least one level of cache memory which is private to the node, a shared, last level cache (LLC) memory device and a shared, last level cache location buffer containing cache location entries, each cache location entry storing an address tag and a plurality of location information. The location information stored in a cache location entry points to an identified cacheline location within the LLC that stores a cacheline associated with the location information. The cacheline stored in the LLC has associated information identifying the cache location entry.

主权项

1. A computer processing system comprising:
a plurality of nodes, each node having at least one processor core and at least one level of cache memory which is private to the node, a shared, last level cache (LLC) memory device; and a shared, last level cache location buffer containing cache location entries, each cache location entry storing an address tag and a plurality of location information, wherein the location information stored in a cache location entry points to an identified cacheline location within the LLC that stores a cacheline associated with the location information, and wherein the cacheline stored in the LLC has associated information identifying the cache location entry.