Method for allocating addresses to data buffers in distributed buffer chipset

摘要

The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.

主权项

1. A method for allocating addresses to data buffers without preconfigured address pins in a distributed buffer chipset, applied in a distributed buffer chipset controlled by a memory controller, wherein the distributed buffer chipset at least comprises:
a central buffer connected to the memory controller through one Command/Address channel (CA); and a plurality of data buffers without preconfigured address pins, wherein each of the plurality of data buffers is respectively connected to the memory controller through a different respective data channel of a plurality of data channels, wherein the data buffers are connected to the central buffer through sharing one data control channel, the method for allocating addresses to data buffers in a distributed buffer chipset comprising: 1) at the memory controller, (i) sending an address allocation start signal to the central buffer through the CA, and (ii) sending a different respective address parameter to each of the plurality of data buffers without preconfigured address pins through each of the plurality of respective data channels; 1-1) at the memory controller, presetting designated time and a specific number; and 1-2) at the memory controller, sending an address allocation start signal to the central buffer through the CA, resetting and starting the time, sending respective address configuration values to the corresponding data buffers through the data channels, and maintaining a state of driving the corresponding address configuration values before the time reaches the preset designated time; 2) at the central buffer, sending the received address allocation start signal to all the data buffers through the data control channel, so as to inform all the data buffers of preparing for receiving the respective address parameters through the respective data channels; and 3) at each data buffer, correspondingly receiving and latching its different respective address parameter through its different respective data channel; 3-1) at each data buffer, correspondingly receiving its address configuration value through the respective data channel and latching its address configuration value by each data buffer; 3-2) at the memory controller, when the time reaches the preset designated time, stopping sending the address configuration values, subtracting 1 from the preset specific number, and judging whether the specific number is 0 after the subtraction of 1, if yes, performing step 3-3); otherwise, returning to the step 1-2); and 3-3) at each data buffer, according to a precedence order of its latched address configuration values, sequentially concatenating its address configuration values to form a respective address parameter with the first latched address configuration value as the lowest bit and with the last latched address configuration value as the highest bit, and ending the allocation process.