Vertical gate stacked NAND and row decoder for erase operation

摘要

A three-dimensional integrated circuit non-volatile memory array includes a memory array with multiple vertical gate NAND memory cell strings formed in a different vertical layers over a substrate which share a common set of word lines, where different groupings of NAND memory cell strings formed between dedicated pairings of source line structures and bit line structures form separately erasable blocks which are addressed and erased by applying an erase voltage to the source line structure of the erase block being erased while applying a ground voltage to the other source line structures in the array and a high pass voltage to the bit line structures in the array.

主权项

1. A three-dimensional non-volatile memory device, comprising:
a memory array comprising a plurality of vertical gate NAND memory cell strings formed in a plurality of different layers over a substrate and sharing a common set of word lines, comprising a first plurality of NAND memory cell strings forming a first erase block and second plurality of NAND memory cell strings forming a second erase block; a first source line structure and one or more first string select structures connected respectively on opposite ends of the first plurality of NAND memory cell strings, where the first source line structure controls erasure of the first erase block; a second source line structure and one or more second string select structures connected respectively on opposite ends of the second plurality of NAND memory cell strings, where the second source line structure controls erasure of the second erase block; and a source line selection circuit for selecting between the first source line structure and the second source line structure when erasing the first erase block or second erase block.