SYSTEM-ON-CHIP DESIGN STRUCTURE

摘要

Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units.

主权项

1. A system-on-chip comprising:
a central processor; a video processor; an audio processor; a graphic processor; and a coherent memory module configured to handle data communications between the central processor, the video processor, the audio processor, and the graphic processor as accesses to memory, the coherent memory module including:
a plurality of first caches, each of the first caches associated with one of the central processor, the video processor, the audio processor, and the graphic processor;a second cache communicatively coupled to each of the plurality of first caches; anda cache controller configured to control the data communications from one or more of the central processor, the video processor, the audio processor, and the graphic processor to other of the central processor, the video processor, the audio processor, and the graphic processor by controlling read and write operations between the plurality of first caches and the second cache.