Thin film transistor array substrate and method for manufacturing the same

摘要

The present disclosure discloses a method for manufacturing a TFT array substrate, comprising: depositing a gate metal layer, a gate insulating layer, a semiconductor layer and a source-drain electrode layer in this order on a base substrate, performing a first photolithograph process to form a common electrode line, a gate line, a gate electrode, a source electrode, a drain electrode and a channel defined between the source electrode and the drain electrode; depositing a passivation layer, performing a second photolithograph process to form a first via hole and a second via hole in the passivation layer; and depositing a pixel electrode layer and a data line layer in this order, perform a third photolithograph process to form a data line connected to the source electrode through the first via hole and a pixel electrode connected to the drain electrode through the second via hole.

主权项

1. A thin film transistor (TFT) array substrate comprising: a base substrate;
a common electrode line, a gate line and a gate electrode formed on the base substrate; a gate insulating layer formed above the common electrode line, the gate line and the gate electrode; a semiconductor layer formed above the gate insulating layer located on the gate electrode; a source electrode and a drain electrode formed above the semiconductor layer with a channel defined between the source electrode and the drain electrode; a passivation layer formed above the base substrate including the common electrode line, the gate line, the gate electrode, the source electrode, the drain electrode and the channel; a pixel electrode layer formed above the passivation layer; a first via hole formed in the passivation layer located above the source electrode; a second via hole formed in the passivation layer located above the drain electrode; a data line comprises a data metal layer and an anti-oxidation material layer formed above the pixel electrode layer, which is connected to the source electrode through the first via hole with the pixel electrode layer interposed therebetween; a pixel electrode comprises the pixel electrode layer which is connected to the drain electrode through the second via hole and the data line is removed on the pixel electrode which is on the drain electrode, wherein the gate line, the gate electrode, the gate insulating layer, the source electrode and the drain electrodes are located in a stack having a trapezium-shaped cross-section.