Apparatus and method for correcting output signal of FPGA-based memory test device

摘要

An apparatus and method for correcting an output signal of an FPGA-based memory test device includes a clock generator for outputting clock signals having different phases; and a pattern generator for outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, and correcting a timing of each of the output signals using flip flops for timing measurement. Wherein the address signal, the data signal and the clock signal, through a pattern generator, are implemented with a programmable logic such as FPGA, thereby shortening the correcting time without the use of an external delay device, and increasing accuracy of output timing of the signal for memory testing, ultimately enhancing performance (accuracy) of a memory tester.

主权项

1. An apparatus for correcting an output signal of a Field Programmable Gate Array (FPGA)-based memory test device, comprising:
a clock generator outputting clock signals having different phases; and a pattern generator outputting an address signal, a data signal and a clock signal in response to the clock signals input from the clock generator, the signals being output by correcting timing of each of the output signals using flip flops for timing measurement, wherein the flip flops includes
a first flip flop and a second flip flop configured to receive the output signals of the pattern generator and the clock signals from the clock generator to output signals to PIN1 and PIN2 corresponding to the clock signals, respectively,a third flip flop provided between the first flip flop and PIN1, anda fourth flip flop provided between the second flip flop and PIN2, and wherein the third flip flop receives the clock signal of the first flip flop and a common clock signal, and the fourth flip flop receives the clock signal of the second flip flop and the common clock signal.