Low leakage retention register tray

摘要

A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.

主权项

1. A circuit comprising:
a first retention register that includes a first non-volatile region and a first volatile region; and a second retention register that includes a second non-volatile region and a second volatile region, wherein the first retention register is coupled to the second retention register, and the second volatile region comprises:
a multiplexer configured to select a shift data signal from the first retention register or an input data signal according to a shift signal; anda volatile retention stage configured to latch the selected one of the shift data signal and the input data signal according to a clock signal; wherein the first non-volatile region and the second non-volatile region are located in a first n-type well (n-well) that is connected to an external voltage source, and wherein the first volatile region and the second volatile region are located in a second n-well that is connected to an internal voltage source.