Register renaming scheme with checkpoint repair in a processing device

摘要

A data processing device maintains register map information that maps accesses to architectural registers, as identified by instructions being executed, to physical registers of the data processing device. In response to determining that an instruction, such as a speculatively-executing conditional branch, indicates a checkpoint, the data processing device stores the register map information for subsequent retrieval depending on the resolution of the instruction. In addition, in response to the checkpoint indication the data processing device generates new register map information such that accesses to the architectural registers are mapped to different physical registers. The data processing device maintains a list, referred to as a free register list, of physical registers available to be mapped to an architectural registers.

主权项

1. A processing device comprising:
a plurality of physical registers; a register map comprising a first map entry that is associated with a first architectural register, the first map entry being adapted to store a first identifier of a first physical register of the plurality of physical registers such that a program instruction that accesses the first architectural register results in an access of the first physical register; a first free register list comprising a first free register entry adapted to store a second identifier for a second physical register of the plurality of physical registers, wherein the second physical register is not mapped to the first architectural register, and wherein the first free register entry includes a valid entry indicator; a first checkpoint map comprising a first checkpoint entry that is associated with the first map entry, wherein the first checkpoint entry is adapted to store the first identifier in response to a first program instruction; a scoreboard comprising a first scoreboard entry that is associated with the first physical register, wherein the first scoreboard entry includes a read counter that indicates a number of outstanding reads to the first physical register, a checkpoint indicator that indicates when the first identifier is stored in the first checkpoint entry, and a free tag indicator to store a location identifier for locating an identifier of a physical register in the first free register list; checkpoint logic adapted to:
determine that the first program instruction results in a first change in execution path of program instructions within the processing device; andin response to determining that the first program instruction specifies the first change in execution path, to:
store the first identifier in the first checkpoint entry;set the checkpoint indicator;store the first identifier at a first location in the first register list in response to storing the first identifier in the checkpoint map;clear the valid entry indicator at the first location in response to storing the first identifier in the first free register list;store a first location identifier associated with the first location in the free tag indicator; andwhen the read counter indicates that the number of outstanding reads to the first physical register is equal to zero:
determine if the checkpoint indicator is set;access the free tag indicator to determine the first location; andset the valid entry indicator at the first location; and a renaming logic adapted to:
determine that a second program instruction that specifies a read operation to the first architectural register is programmed to be executed before a third program instruction that specifies a write operation to the first architectural register, and that the second program instruction is pending execution by an out-of-order execution engine of the processing device after the third program instruction is executed by the execution engine; andin response to determining that the second program instruction will be executed after the third program instruction store the second identifier in the first map entry such that a program instruction that accesses the first architectural register is mapped to the second physical register.